Three-dimensional (3D) system integration has emerged as a key enabling technology to continue the scaling trajectory that Moore's Law predicted for future integrated circuit (IC) generations. More particularly, with 3D integration technology, components in a stacked IC can be placed on different dies, which can substantially reduce both the average and maximum distance between the components in the stacked IC and translate into significant savings in delay, power, and area footprint. Furthermore, 3D integration technology can enable the integration of heterogeneous devices, thereby making the entire system more compact and more efficient. Nevertheless, the success of 3D stacked ICs is predicated on the final post-bond yield, i.e., minimizing the number of good dies that are bonded to defective dies. As such, the overall yield of 3D ICs improves with pre-bond testing, which involves testing each individual die in a 3D stacked IC prior to the bonding process, because manufacturers can avoid stacking defective dies with good dies.
However, pre-bond testability presents unique challenges to 3D clock tree design. For example, each individual die in a 3D stacked IC generally needs a complete 2D clock tree to enable pre-bond testing because the clock signal has to reliably span across multiple tiers under tight skew and slew constraints. Furthermore, the entire 3D stack needs a complete 3D clock tree for post-bond testing and post-bond operation. A straightforward solution may simply have a complete 2D clock tree on each individual die and use a single through-silicon-via (TSV) to connect the 2D clock trees on adjacent die. However, the single TSV solution suffers from various drawbacks, which include long wirelength (WL) and high clock power consumption because more buffers are needed. Further, in a 3D stacked IC where one backbone die has a single large clock tree and all other dies have multiple small trees that are not connected to one another, the backbone die with the single tree needs only one clock probe during pre-bond testing, but all other dies need multiple probes, which can complicate testing. Another proposed approach to the pre-bond testing problem in 3D stacked ICs uses multiple TSVs to connect the backbone die to the non-backbone die and adding an extra redundant tree (or R-Tree) to connect the small trees in the non-backbone die such that a single clock probe can be used for pre-bond testing. Although the R-tree may simplify pre-bond testability, the R-tree tends to have a significant design-for-testing (DFT) cost because transmission gates are used to detach the R-tree from the small trees after pre-bond testing, which requires an extra global connection to turn off the transmission gates, thereby adding to the total DFT cost.